The present invention relates to a manufacturing method of a semiconductor device, and to a manufacturing method of a semiconductor device which has a size approximately same as a semiconductor chip when viewed in a plan view, and in which the semiconductor chip is flip-chip bonded to a wiring pattern.
Among conventional semiconductor devices, there is a semiconductor device, called a chip-size package (see FIG. 1, for example) which is made in almost the same size as the size of a semiconductor chip when viewed in a plan view.
FIG. 1 is a cross-sectional view of a conventional semiconductor device.
With reference to FIG. 1, a conventional semiconductor device 100 includes a semiconductor chip 101, internal connection terminals 102, a resin layer 103, a wiring pattern 104, a solder mask 106, and external connection terminals 107.
The semiconductor chip 101 includes a semiconductor substrate 110 which has been thinned, a semiconductor integrated circuit 111, a plurality of electrode pads 112 and a protective film 113. The semiconductor integrated circuit 111 is provided on the top surface of the semiconductor substrate 110. The semiconductor integrated circuit 111 includes a diffused layer(s), insulating layer(s), via(s) and wire(s) and the like. The plurality of electrode pads 112 are provided over the semiconductor integrated circuit 111. The plurality of electrode pads 112 are electrically connected to the wires provided on the semiconductor integrated circuit 111. The protective film 113 is provided over the semiconductor integrated circuit 111. The protective film 113 is a film for protecting the semiconductor integrated circuit 111.
The Internal connection terminals 102 are provided on the electrode pads 112. The top ends of the internal connection terminals 102 are exposed from the resin layer 103. The top ends of the internal connection terminals 102 are connected to the wiring pattern 104. The resin layer 103 is provided so as to cover the surface of the semiconductor chip 101 on which the internal connection terminals 102 are provided.
The wiring pattern 104 is provided on the resin layer 103. The wiring pattern 104 is connected to the internal connection terminals 102. The wiring pattern 104 is electrically connected to the electrode pads 112 via the internal connection terminals 102. The wiring pattern 104 has external connection terminal formation regions 104A on which the external connection terminals 107 are provided. The solder mask 106 is provided over the resin layer 103 so as to cover a portion of the wiring pattern 104 other than the external connection terminal formation regions 104A.
FIGS. 2 through 10 show manufacturing steps of the conventional semiconductor device. In FIGS. 2 through 10, identical constituents are denoted by the same reference numerals as in the conventional semiconductor device 100 shown in FIG. 1.
First, in a process step shown in FIG. 2, over the semiconductor substrate 110 which has not yet been thinned, the semiconductor chip 101 including the semiconductor integrated circuit 111, the plurality of electrode pads 112 and the protective film 113 is formed. Next, in a process step shown in FIG. 3, the internal connection terminals 102 are formed on the plurality of the electrode pads 112. At this point of time, the plurality of internal connection terminals 102 vary in their heights.
Next, in a process step shown in FIG. 4, a flat plate 115 is pressed against the plurality of internal connection terminals 102 to align the heights of the internal connection terminals 102. Then, in the step shown in FIG. 5, the resin layer 103 is formed so as to cover the internal connection terminals 102 and a surface of the semiconductor chip 101 on which the internal connection terminals 102 are formed.
Next, in a process step shown in FIG. 6, the resin layer 103 is ground until the top surfaces 102A of the internal connection terminals 102 are exposed from the resin layer 103. At this point of time, the grinding is done so as to make the top surface 103A of the resin layer 103 approximately flush with the top surfaces 102A of the internal connection terminals 102.
Next, in a process step shown in FIG. 7, the wiring pattern 104 is formed over the top surface 103A of the resin layer 103. Next, in a step shown in FIG. 8, the solder mask 106 is formed on the resin layer 103 so as to cover the portion of the wiring pattern 104 other than the external connection terminal formation regions 104A.
Next, in a process step shown in FIG. 9, the semiconductor substrate 110 is ground from the bottom side of the semiconductor substrate 110 to make the semiconductor substrate 110 thinner. Next, in a process step shown in FIG. 10, the external connection terminals 107 are formed over the external connection terminal formation regions 104A. In this way, the semiconductor device 100 is completed (see the Patent Document 1).
[Patent Document 1] Japanese Patent No. 3,614,828
However, the manufacturing method of the conventional semiconductor device 100 requires the process to align the heights of the plurality of internal connection terminals 102 and the process to expose the top surfaces 102A of the plurality of internal connection terminals 102 from the resin layer 103 by grinding the resin layer 103, so that there has been a problem that many process steps are required, thereby increasing the manufacturing cost.